Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/12281
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dc.contributor.authorKalganova, T-
dc.contributor.authorLipnitskaya, N-
dc.contributor.authorYatskevich, Y-
dc.coverage.spatialNottingham, United Kingdom-
dc.coverage.spatialNottingham, United Kingdom-
dc.date.accessioned2016-03-07T12:04:53Z-
dc.date.available2016-03-07T12:04:53Z-
dc.date.issued2004-
dc.identifier.citationProceedings of the 5th International Conference on Recent Advances in Soft Computing, Nottingham, UK, 01 December 2004, pp. 466 - 471en_US
dc.identifier.isbn1-84233-110-8-
dc.identifier.urihttp://bura.brunel.ac.uk/handle/2438/12281-
dc.description.abstractThis paper proposes a new evolvable hardware (EHW) technique that allows one to design and optimise relatively complex PLA structures using direct evolutionary process. In order to improve the performance of the evolutionary strategy the authors proposed to introduce the dynamic mutation rate that will be variable to each gene in the chromosome. The experimental results carried out on MCNC benchmarks show that the developed technique significantly outperforms any standard evolvable hardware technique introduced earlier by a number of criteria: time required to evolve logic circuit; evolution of complex circuit using only one direct evolutionary process; guarantee of evolution of fully functional solution.en_US
dc.format.extent466 - 471-
dc.language.isoenen_US
dc.subjectEvolvable hardwareen_US
dc.subjectPLAen_US
dc.subjectEvolutionary computationen_US
dc.titleEvolving PLA structures using evolutionary strategy with dynamic mutation rateen_US
dc.typeConference Paperen_US
dc.relation.isPartOfProceedings of the 5th International Conference on Recent Advances in Soft Computing-
pubs.publication-statusPublished-
pubs.publication-statusPublished-
pubs.start-date2004-12-01-
pubs.start-date2004-12-01-
Appears in Collections:Dept of Electronic and Electrical Engineering Research Papers

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