Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/9294
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dc.contributor.authorSharma, CS-
dc.contributor.authorTiwari, MK-
dc.contributor.authorPoulikakos, D-
dc.contributor.author4th Micro and Nano Flows Conference (MNF2014)-
dc.date.accessioned2014-12-02T16:02:56Z-
dc.date.available2014-12-02T16:02:56Z-
dc.date.issued2014-
dc.identifier.citation4th Micro and Nano Flows Conference, University College London, UK, 7-10 September 2014, Editors CS König, TG Karayiannis and S. Balabanien_US
dc.identifier.isbn978-1-908549-16-7-
dc.identifier.urihttp://bura.brunel.ac.uk/handle/2438/9294-
dc.descriptionThis paper was presented at the 4th Micro and Nano Flows Conference (MNF2014), which was held at University College, London, UK. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute, ASME Press, LCN London Centre for Nanotechnology, UCL University College London, UCL Engineering, the International NanoScience Community, www.nanopaprika.eu.en_US
dc.description.abstractHotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip. These in turn adversely affect the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a 1-dimensional model for quick design of a microchannel heat sink for targeted, single-phase liquid cooling of hotspots in microprocessors. The method utilizes simplifying assumptions and analytical equations to arrive at the first estimate of a microchannel heat sink design that distributes the cooling capacity of the heat sink by adapting the coolant flow and microchannel size distributions to the microprocessor power map. This distributed cooling in turn minimizes the chip temperature gradient. The method is formulated to generate a heat sink design for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of microchannel widths for various zones of the chip power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting first design estimate significantly reduces the computational effort involved in any subsequent CFD analysis required to fine tune the design for more complex flow situations arising, for example, in manifold microchannel heat sinks.en_US
dc.language.isoenen_US
dc.publisherBrunel University Londonen_US
dc.relation.ispartofseriesID 39-
dc.subjectMicrochannelsen_US
dc.subjectHotspot-targeted coolingen_US
dc.subjectElectronics coolingen_US
dc.subjectHotspotsen_US
dc.titleOptimal microscale water cooled heat sinks for targeted alleviation of hotspot in microprocessorsen_US
dc.typeConference Paperen_US
Appears in Collections:Brunel Institute for Bioengineering (BIB)
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