Parallelised max-log-MAP model

Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/3626

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DC Field	Value	Language
dc.contributor.author	Loo, KK	-
dc.coverage.spatial	2	en
dc.date.accessioned	2009-09-23T12:43:35Z	-
dc.date.available	2009-09-23T12:43:35Z	-
dc.date.issued	2002	-
dc.identifier.citation	Electronics Letters 38(17): 971-972, Aug 2002	en
dc.identifier.issn	0013-5194	-
dc.identifier.uri	http://bura.brunel.ac.uk/handle/2438/3626	-
dc.description.abstract	A paralleliscd max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architccture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model rcduccs considerably thc computational complexity of the max-Log-MAP algorithm; valid therefore facilitates easy implementation.	en
dc.format.extent	249789 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.publisher	IEEE	en
dc.relation.ispartof	38;17	-
dc.subject	Turbo code	en
dc.subject	DSP	en
dc.subject	Implementation	en
dc.subject	Max-log-map	en
dc.title	Parallelised max-log-MAP model	en
dc.type	Research Paper	en
Appears in Collections:	Electronic and Computer Engineering Dept of Electronic and Electrical Engineering Research Papers

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