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http://bura.brunel.ac.uk/handle/2438/2988
Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Shankar, A | - |
dc.contributor.author | Gilbert, D | - |
dc.contributor.author | Jampel, M | - |
dc.coverage.spatial | 10 | en |
dc.date.accessioned | 2009-01-29T13:07:41Z | - |
dc.date.available | 2009-01-29T13:07:41Z | - |
dc.date.issued | 1996 | - |
dc.identifier.citation | Proceedings of INAP-96: The 9th Symposium and Exhibition on Industrial Applications of Prolog, Tokyo, Japan, 16-19 October 1996. | en |
dc.identifier.uri | http://bura.brunel.ac.uk/handle/2438/2988 | - |
dc.description.abstract | In this paper describes the design of a transient analysis program for linear circuits and its implementation in a Constraint Logic Programming language, CLP(R). The transient analysis program parses the input circuit description into a network graph, analyses its semantic correctness and then performs the transient analysis. The test results show that the program is at least 97% accurate when run at two decimal places. We have also compared the performance of our program with a commercial package implemented in an imperative language. The advantages of implementing the analysis program in a CLP language include: quick construction and ease of maintenance. We also report on the synthesis of generation of a circuit with given transient characteristics. | en |
dc.format.extent | 60883 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | INAP | en |
dc.title | Transient analysis and synthesis of linear circuits using constraint logic programming | en |
dc.type | Conference Paper | en |
Appears in Collections: | Computer Science Dept of Computer Science Research Papers |
Files in This Item:
File | Description | Size | Format | |
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10.1.1.46.993.pdf | 59.46 kB | Adobe PDF | View/Open |
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