A two-dimension time-domain comparator for low power SAR ADCs

Abstract

This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register (SAR) analog-to-digital converters (ADCs). The proposed two-dimension time-domain comparator consists of a ring oscillator collapse-based comparator and a counter. The propagation delay of a voltage controlled ring oscillator depends on the input. Thus, the comparator can automatically change the comparison time according to its input difference, which can adjust the power consumption of the comparator dynamically without any control logic. And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small. Thus, the proposed comparator can not only provide the polarity of the input, but also the amount information of the input, which helps to skip most of the SAR cycles when the initial input is small. Thus, most energy can be saved when the initial input is small. The proposed time-domain comparator is designed in 0.18 μm CMOS technology. Simulation results demonstrate that the comparator can not only save power consumption, but also give the design flexibility, and the current is only nA level when the supply voltage is 0.6 V.