A practical WSI experimental programme

Jalowiecki, IP; Hedge, SJ; Lea, RM

Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/1646

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DC Field	Value	Language
dc.contributor.author	Jalowiecki, IP	-
dc.contributor.author	Hedge, SJ	-
dc.contributor.author	Lea, RM	-
dc.coverage.spatial	3	en
dc.date.accessioned	2008-02-15T10:57:14Z	-
dc.date.available	2008-02-15T10:57:14Z	-
dc.date.issued	1991	-
dc.identifier.citation	IEE Colloquium on Wafer Scale Integration, London, UK, pp. 7/1-7/3, May 1991	en
dc.identifier.uri	http://bura.brunel.ac.uk/handle/2438/1646	-
dc.description.abstract	At Brunel University, research has been underway for several years to assess the architectural, electrical and physical benefits and constraints of the WASP wafer-scale Associative String Processor (ASP). This is intended to implement a massively parallel processor entirely within the constraints of WSI. WASP 1 and WASP 2 were the technology demonstrators of the UK funded Alvey programme (starting 1984), researching fundamental design methodologies for WSI. They are both examples of the Associative String Processor (ASP) architecture, developed by Brunel University. Further demonstrators are currently funded by a 31/2-year US ONR IS&T programme (starting 1987), involving both further technology demonstration, applications research and fundamental packaging and manufacturing design issues	en
dc.format.extent	185724 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.publisher	IEEE	en
dc.subject	VLSI	en
dc.subject	Microprocessor chips	en
dc.subject	Parallel architectures	en
dc.title	A practical WSI experimental programme	en
dc.type	Research Paper	en
Appears in Collections:	Electronic and Computer Engineering Dept of Electronic and Electrical Engineering Research Papers

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