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http://bura.brunel.ac.uk/handle/2438/1646| Title: | A practical WSI experimental programme |
| Authors: | Jalowiecki, IP Hedge, SJ Lea, RM |
| Keywords: | VLSI;Microprocessor chips;Parallel architectures |
| Issue Date: | 1991 |
| Publisher: | IEEE |
| Citation: | IEE Colloquium on Wafer Scale Integration, London, UK, pp. 7/1-7/3, May 1991 |
| Abstract: | At Brunel University, research has been underway for several years to assess the architectural, electrical and physical benefits and constraints of the WASP wafer-scale Associative String Processor (ASP). This is intended to implement a massively parallel processor entirely within the constraints of WSI. WASP 1 and WASP 2 were the technology demonstrators of the UK funded Alvey programme (starting 1984), researching fundamental design methodologies for WSI. They are both examples of the Associative String Processor (ASP) architecture, developed by Brunel University. Further demonstrators are currently funded by a 31/2-year US ONR IS&T programme (starting 1987), involving both further technology demonstration, applications research and fundamental packaging and manufacturing design issues |
| URI: | http://bura.brunel.ac.uk/handle/2438/1646 |
| Appears in Collections: | Electronic and Computer Engineering Dept of Electronic and Electrical Engineering Research Papers |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| A PRACTICAL WSI EXPERIMENTAL PROGRAMME.pdf | 181.37 kB | Adobe PDF | View/Open |
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