Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/12345
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dc.contributor.authorLambert, C-
dc.contributor.authorKalganova, T-
dc.contributor.authorStomeo, E-
dc.contributor.authorWilson, M-
dc.date.accessioned2016-03-14T11:52:36Z-
dc.date.available2007-
dc.date.available2016-03-14T11:52:36Z-
dc.date.issued2007-
dc.identifier.citationInternational Journal of Computational Intelligence, 3, (3): p. 276, (2007)en_US
dc.identifier.issn3-
dc.identifier.issn3-
dc.identifier.issn1304-4508-
dc.identifier.urihttp://connection.ebscohost.com/c/articles/31704158/multi-board-run-time-reconfigurable-implementation-intrinsic-evolvable-hardware-
dc.identifier.urihttp://bura.brunel.ac.uk/handle/2438/12345-
dc.description.abstractThis paper is devoted to present a multi-board run-time reconfigurable (MRTR) system for evolvable hardware (EHW) and it is introduced with the aim to implement on hardware the bidirectional incremental evolution (BIE) method. The main features of this digital intrinsic EHW solution rely on the multi-board approach, the variable chromosome length management and the partial configuration of the reconfigurable circuit. These three features provide a high scalability to the solution. The design has been written in VHDL with the concern of not being platform dependant in order to keep a flexibility factor as high as possible. This solution helps tackling the problem of evolving complex task on digital configurable support. Furthermore some experiments are exposed and commented.en_US
dc.language.isoenen_US
dc.publisherWorld Academy of Science, Engineering and Technologyen_US
dc.titleMulti-board run-time reconfigurable implementation of intrinsic evolvable hardwareen_US
dc.typeArticleen_US
dc.relation.isPartOfInternational Journal of Computational Intelligence-
pubs.volume3-
Appears in Collections:Dept of Electronic and Electrical Engineering Research Papers

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