Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/12223
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dc.contributor.authorGutub, AA-A-
dc.contributor.authorSavaş, E-
dc.contributor.authorKalganova, T-
dc.date.accessioned2016-03-02T10:34:46Z-
dc.date.available2006-02-01-
dc.date.available2016-03-02T10:34:46Z-
dc.date.issued2006-
dc.identifier.citationIEEE International Conference on Computer & Communication Engineering, Kuala Lumpur, Malaysia, 09-11 May 2006en_US
dc.identifier.uriwww.iiu.edu.my/iccce06/-
dc.identifier.urihttp://bura.brunel.ac.uk/handle/2438/12223-
dc.description.abstractThis paper accelerates a scalable GF(p) Montgomery inversion hardware. The hardware is made of two parts a memory and a computing unit. We modified the original memory unit to include parallel shifting of all bits which was a task handled by the computing unit. The new hardware modeling, simulating, and synthesizing is performed through VHDL for several 160-bits designs showing interesting speedup to the inverse computation.en_US
dc.description.sponsorshipBritish council in Saudi Arabia, KFUPM, Electrical & Computer Engineering Department of Brunel University in Uxbridgeen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.sourceICCCE '06-
dc.sourceICCCE '06-
dc.subjectMontgomery inverseen_US
dc.subjectElliptic curve cryptographyen_US
dc.subjectScalable hardware designen_US
dc.titleScalable VLSI design for fast GF (p) montgomery inverse computationen_US
dc.typeConference Paperen_US
dc.relation.isPartOfIEEE International Conference on Computer & Communication Engineering-
pubs.finish-date2006-05-11-
pubs.finish-date2006-05-11-
pubs.publication-statusPublished-
pubs.publication-statusPublished-
pubs.start-date2006-05-09-
pubs.start-date2006-05-09-
Appears in Collections:Dept of Electronic and Electrical Engineering Research Papers

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